Skip to main content

Scott Hauck

VLSI and Digital Systems
307Q ECE
185 Stevens Way
University of Washington
Seattle, WA 98195

Phone: 206-412-1523


He is a Professor at the University of Washington's Department of Electrical & Computer Engineering, in the Embedded Systems and VLSI group, and an Adjunct in the Department of Computer Science and Engineering. His work is focused around FPGAs, chips that can be programmed and reprogrammed to implement complex digital logic. His interests are the application of FPGA technology to situations that can make use of their novel features: high-performance computing, reconfigurable subsystems for system-on-a-chip, computer architecture education, hyperspectral image compression, and other areas. His work encompasses VLSI, CAD, and applications of these devices. He recieved his BS in EECS from the University of California - Berkely in 1990, and his MS and Ph.D. in CSE from the University of Washington in 1992 and 1995 respectively. He is editor (with Andre' DeHon) of a book on reconfigurable computing: Scott Hauck, Andre' DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

Awards and Honors

2015 Gaetano Borriello Professorship for Educational Excellence.
IEEE Fellow, 2015, for contributions to Field-Programmable Gate Array based systems.

FCCM20: Highlights of the First Twenty Years of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2013. 4 of 25 papers in this volume - most of any author:

  • S. Hauck, T. W. Fry, M. M. Hosler, J. P. Kao, "The Chimaera Reconfigurable Functional Unit", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, 1997.
  • S. Hauck, Z. Li, E. J. Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 138-146, 1998.
  • Z. Li, K. Compton, S. Hauck, "Configuration Cache Management Techniques for FPGAs", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 22-36, 2000.
  • P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, D. Zaretsky, "A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems", IEEE Symposium on FPGAs for Custom Computing Machines, pp. 39-48, 2000.
IEEE Symposium on Field-Programmable Custom Computing Machines, Best Paper Award, 2012
2011 U.W. Dept. of Electrical Engineering Faculty Service Award
2010 University of Washington Distinguished Teaching Award
2009 College of Engineering Faculty Innovator: Teaching & Learning
Finalist, U.W. Distinguished Teaching Award, 2008
Best Paper Award, Microelectronic Systems Education Conference, 2007.
Elixent, Inc. S.O.A.P.-Star: Spot On Award Program (employee achievement award), 2006.
Alfred P. Sloan Research Fellow (2001)
U.W. EE Department's Outstanding Research Advisor Award 2001
Senior Member, ACM (2009)
Senior Member, IEEE (2001)
June and Donald Brewer Junior Professorship, (Northwestern chair, given up in move to U.W.) 1999-2001
NSF CAREER award (1999)
1999 IEEE Circuits and Systems Society Transactions on VLSI Systems Best Paper Award
Northwestern University, ECE Department's Best Teacher of 1998/99
AT&T Bell Laboratories Graduate Fellowship
National Merit Finalist
Nominated, U.W. College of Engineering Faculty Innovator for Teaching, 2007, 2008, 2009.
Nominated, U.W. Distinguished Teaching Award, 2004, 2007, 2008, 2009
Nominated, U.W. College of Engineering Outstanding Faculty Member, 2004
Nominated, U.W. EE Department's Faculty Service Award, 2004
Nominated, U.W. EE Department's Outstanding Research Advisor Award 2003, 2004, 2008, 2009
Nominated, U.W. EE Department's Teaching Award 2001, 2003, 2007

Honors to students/advisees

College of Engineering Community Innovators Teaching Assistant Innovator Award to Ken Eguro (2008)
Department of Electrical Engineering Graduate Teaching Award to Ken Eguro (2007)
Yang Research Award to Akshay Sharma (2005), Mike Haselman (2010).
Mary Gates Endowment for Students research training grant to Henry Lee (2003)
Intel Fellowship to Mark Chang (2002)
Lincoln Labs Fellowship to Shawn Phillips (2002)
Cabell Thesis Year Fellowship to Katherine Compton (2002)
U.W. EE Department's Outstanding Research Assistant Award to Mark Chang (2001-2002)
National Science Foundation Fellowships to Katherine Compton (1998), Mark Holland (2001), Nathaniel McVicar (2011)
1999 Motorola UPR Best Paper Award (to student Katherine Compton)
National Science Foundation Fellowship Honorable Mention to Michael Beauchamp (2003 & 2004), Nathaniel McVicar (2010)

Research Projects

  • Large Hadron Collider Electronics
    Ongoing development efforts on FPGA-based detector electronics for the Large Hadron Collider at CERN in Europe. This includes efforts on the RD53A emulator.
  • HLS4ML
    Development of techniques for using High-Level Synthesis for Machine Learning tasks, especially the automatic mapping of neural networks to FPGAs.
    Development of a high-speed camera pipeline that uses FPGA-based neural network logic to understand and control crystal growth and other high-speed/low-latency science applications.
  • FPGA Support for Quantum Computing
    Creation of high-speed signal generators for laser control within a quantum computer.


(Surveys and introductory articles for a general audience)

Full list of publications

S. Hauck, A. DeHon (editors), Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation", Morgan Kaufmann/Elsevier, 2008.

S. Hauck, "Asynchronous Design Methodologies: An Overview" (PDF), Proceedings of the IEEE, Vol. 83, No. 1, pp. 69-93, January, 1995.

S. Hauck, "The Roles of FPGAs in Reprogrammable Systems" (PDF), Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998.

S. Hauck, "The Future of Reconfigurable Systems" (PDF), Keynote Address, 5th Canadian Conference on Field Programmable Devices, Montreal, June 1998.

S. Hauck, A. Agarwal, "Software Technologies for Reconfigurable Systems" (PDF), Northwestern University, Dept. of ECE Technical Report, 1996.

K. Compton, S. Hauck, "Reconfigurable Computing: A Survey of Systems and Software" (PDF), ACM Computing Surveys, Vol. 34, No. 2. pp. 171-210. June 2002.

S. Hauck, K. Compton, K. Eguro, M. Holland, S. Phillips, A. Sharma, "Totem: Domain-Specific Reconfigurable Logic", 2006.

M. Haselman, S. Hauck, "The Future of Integrated Circuits: A Survey of Nano-electronics", Proceedings of the IEEE, Vol. 98, No. 1, pp. 11-38, January 2010.

Allison Deiana et al, "Applications and Techniques for Fast Machine Learning in Science", Frontiers in Big Data, 2022.


Current Graduate Students

  • Rajeev Botadra (M.S. expected Spring '25)
    High-Speed Machine Learning on FPGAs for Neural Data Processing.
  • Hongjiang Cai (PMP M.S. expected Spring '24)
    FPGA Support for the Large Hadron Collider.
  • Katharine Lundblad (M.S. expected Spring '25)
    High-Performance FPGA-based Readout for a Quantum Computer.
  • Atharva Mattam (M.S. expected Spring 2024)
    Efficient Gaussian Random Number Generators in HLS4ML.
  • Pranav Srinivas Murali (M.S. expected Spring '24)
    FPGA Support for the Large Hadron Collider.
  • Yilin Shen (M.S. expected Spring '24)
    Efficient Support of HLS4ML Flows within the Xilinx ACAP Architecture
  • Gayathri Vadhyan (M.S. expected Spring '25)
    FPGA Support for the Large Hadron Collider.
  • Dennis Yin (M.S. expected Spring '25)
    Efficient Transformer Support in HLS4ML.
  • Haochen "Eric" Yu (M.S. expected Spring '25)
    FPGA-based Control for Quantum Computing.

Former Graduate Students

  • Morgan Enos, M.S., "Replication for Logic Partitioning", September 1996. Consultant.
  • Oliver Stone, M.S., "A Comparison of ASIC Implementation Alternatives", October 1996. Joined Digital Equipment Corp.
  • Matt Hosler, M.S., "High-Performance Carry Chains for FPGAs", October 1997. Joined Motorola, then Arrow Electronics.
  • Guangyu Gu, M.S., "Accelerating Photoshop Applications with Reconfigurable Hardware", May 1999. Joined United Airlines, then Microsoft.
  • Venkatesh Karnam, M.S., "Applications of Reconfigurable Logic", March 2000. Joined Yahoo.
  • Thomas Fry, M.S., "Hyperspectral Image Compression on Reconfigurable Platforms", June 2001. Joined IBM, then went for MBA.
  • Melany Richmond, M.S., "A Lemple-Ziv based Configuration Management Architecture for Reconfigurable Computing", July 2001. Joined Quicksilver, then Zilog, then Cypress.
  • Chandra Mulpuri, M.S., "Runtime and Quality Tradeoffs in FPGA Placement and Routing", July 2001. Joined NEC, then Velogix, then Xilinx.
  • Zhiyuan Li, Ph.D., "Configuration Management for Reconfigurable Systems", November 2001. Joined Motorola.
  • Katherine Compton, M.S., "Programming Architectures for Run-Time Reconfigurable Systems", Fall 1999. Ph.D. "Architecture Generation of Customized Reconfigurable Hardware", September 2003. Faculty at University of Wisconsin - Madison.
  • Todd Owen, M.S. "FPGA Implementation of Error Correction and Improved SPIHT Compression for NASA Hyperspectral Images", June 2003. Joined Intel.
  • Kimberly Motonaga, M.S. "Encryption RaPiD: A Comparison of Custom and Standard-Cell Designs", December 2003. Joined Boeing.
  • Brigette Huang, M.S. 2D FPGA Layout, 2004. Joined Microsoft.
  • Mark Chang, M.S., "Adaptive Computing in NASA Multi-Spectral Image Processing", 1999. Ph.D., "Variable Precision Analysis for FPGA Synthesis", 2004. Faculty at Olin College, then EdX, then Google.
  • Shawn Phillips, M.S. "Automatic Layout of Domain Specific Reconfigurable Subsystems for System-on-a-Chip", 2001. Ph.D. "Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip", 2004. Joined Annapolis Microsystems, then Johns Hopkins University - Applied Physics Lab.
  • Akshay Sharma, M.S. "Development of a Place and Route Tool for the RaPiD Architecture". Ph.D. "Place and Route Techniques for FPGA Architecture Advancement", 2005. Joined Actel, then Lecturer at the University of Washington, then Sun/Oracle.
  • Mark Holland, M.S. "Harnessing FPGAs for Computer Architecture Education, 2002. Ph.D. Automatic Creation of Product-Term-Based Reconfigurable Architectures for System-on-a-Chip, June 2005. Joined Annapolis Microsystems.
  • Mike Beauchamp, M.S. "Architectural Modifications to Enhance the Floating-Point Performance of FPGAs", August 2006. Joined MIPS.
  • Peter Grossman, M.S. "Architecture-Adaptive FPGA Placment", December 2006. Joined MIT Lincoln Labs.
  • Don DeWitt, M.S. "An FPGA Implementation of Statistical Based Positioning for Positron Emission Tomography", June 2008. Contractor with U.W. Dept. of Radiology.
  • Allan Carroll, M.S. "Characterizing the Quality of QuickRoute, A Heuristic Pipeline Router", Summer 2008. Joined
  • Ken Eguro, M.S. "Encryption-Specific FPGA Architectures", Fall 2002. Ph.D. "Supporting High-Performance Pipelined Computation in Commodity-Style FPGAs", November 2008. Joined Microsoft Research.
  • Nikhil Subramanian, M.S. "A C-to-FPGA Solution for Accelerating Tomographic Reconstruction", Spring 2009. Joined Microsoft.
  • Nathan Johnson-Williams, M.S. "Design of a Real Time FPGA-based Three Dimensional Positioning Algorithm", Fall 2009. Joined Sandia National Labs, then Aerospace Corp, then New Wave Design and Verification.
  • Ziyuan Zhang, M.S. Winter 2010. Joined Bonneville Power Administration.
  • Jimmy Xu, M.S. Winter 2010. Joined Apple.
  • Ben Ylvisaker, Ph.D. Autumn 2011. Joined Grammatech Inc, then Swarthmore College, then Colorado College, then Altia.
  • Brian Van Essen, Ph.D. Autumn 2011. Joined Lawrence Livermore National Labs.
  • Adam Knight, M.S. "Multi-Kernel Macah Support and Applications", Autumn 2011. Joined Intel.
  • Abhishek Raja, M.S. Autumn 2011. Joined AMD.
  • Mike Haselman, M.S. "Bitwidth Analysis of Floating-Point Computations for FPGA Implementations", Spring 2005. Ph.D. "FPGA-Based Pulse Processing for Positron Emission Tomography", Spring 2011. Joined Sandia National Labs, then Microsoft.
  • Corey Olson, M.S. "An FPGA Acceleration of Short Read Human Genome Mapping", Spring 2011. Joined Pico Computing.
  • Maria Kim, M.S. "Accelerating Next Generation Genome Reassembly in FPGAs: Alignment Using Dynamic Programming Algorithms", Spring 2011. Joined ITT Tech, then Boeing.
  • Stephen Friedman, Ph.D. "Resource Sharing in Modulo-Scheduled Reconfigurable Architectures", Summer 2011. Joined Pixar.
  • James Pasko, M.S. Winter 2011. Joined Google.
  • Andrew Price, M.S. "Hephaestus: Solving the Heterogeneous, Highly Constrained Analog Placement Problem", Winter 2012. Joined Cypress.
  • Marshal Barrett, M.S. Winter 2013. Joined Garmin.
  • Shaw-Pin "Bing" Chen, M.S. "Readout Driver Firmware Development for the ATLAS Insertable B-Layer", Spring 2014. Joined Ario.
  • Joseph Mayer, M.S. "Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector", Spring 2016. Joined Wolverine Trading, then Microsoft.
  • Arushi Sonkhya, M.S. Spring 2016. Joined Philips HealthTech.
  • Aaron Wood, Ph.D. i"Offset Pipelining for Coarse Grain Reconfigurable Arrays", Winter 2017. Joined Synopsys.
  • Logan Adams, M.S. Spring 2017. Joined Microsoft.
  • Lev Kurilenko, M.S. "FPGA Development of an Emulator Framework and a High Speed I/O Core for the ITk Pixel Upgrade", Spring 2018. Joined Lattice Semiconductor, then Microsoft.
  • Umaymah Khan, M.S. Spring 2018. Joined Microsoft.
  • Nicholas Robillard, M.S. Spring 2018. Joined Blue Origin.
  • Nathaniel McVicar, M.S. "Architecture and Compiler Support for a VLIW Execution Model on a Coarse-Grained Reconfigurable Array", Autumn 2011. Ph.D. "FPGA Accelerated Bioinformatics: Alignment, Classification, Homology and Counting", Autumn 2018. Joined Microsoft.
  • Dustin Werran, M.S. "Development of an FPGA Emulator for the RD53A Test Chip", Winter 2019. Joined Micron, then Two Sigma.
  • Douglas Smith, M.S. "FPGA Development of an Emulator of the RD53A Prototype Chip and its Integration with Various Readout Systems", Spring 2019. Joined Phytec.
  • Richa Rao, M.S. M.S. “Implementation of Long Short-Term Memory Neural Networks in High-Level Synthesis Targeting FPGAs”, Spring 2020. Joined Intel.
  • Niharika Mittal, M.S. “Development of an FPGA Emulator for the RD53B Chip”, Spring 2020. Joined Microsoft.
  • Donavan Erickson, M.S. "Development of a High-Speed Hit Decoder for the RD53B Chip", Spring 2021. Joined Micron.
  • Kelvin Lin, M.S. "Convolutional Layer Implementations in High-Level Synthesis for FPGAs", Spring 2021. Joined Amazon.
  • Chaitanya Paikara, M.S. Spring 2021. Joined nVidia.
  • Matt Trahms, M.S. "Generalized Machine Learning Quantization Implementation for High Level Synthesis Targeting FPGAs", Winter 2022. Joined Micron, then Ampere Computing.
  • Anatoliy Martnyuk, M.S. "Rapid Synchronization Recovery from Single Event Effects in the Large Hadron Collider", Spring 2022. Joined Amazon.
  • Sanjukta Roychoudhury, M.S. "FPGA Design Upgrades for the ATLAS Pixel Readout System in the Large Hadron Collider", Spring 2023. Joined ARM.
  • Xiaohan Liu, M.S. "FPGA Deployment of LFADS for Real-time Neuroscience Experiments", Summer 2023.
  • Caroline Johnson, M.S. "Evaluating the Quality of HLS4ML’s Basic Neural Network Implementations on FPGAs", Autumn 2023. Joined stealth startup.
  • Waiz Khan, M.S. "Quantifying the Performance and Resource Usage of HLS4ML’s Implementation of the Batch Normalization Layer on FPGAs", Winter 2024. Joined Honeywell.