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Visvesh Sathe

Assistant Professor
Biosystems, Computing and Networking
M314 ECE
Campus Box 352500
University of Washington
Seattle, WA 98195
Phone: 206-543-7635
Email: sathe@ece.uw.edu
External Web Page: psylab.ece.uw.edu


Biography

Visvesh Sathe joined the University of Washington Department of Electrical & Computer Engineering in 2013. Prior to joining the faculty at the UW, he served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and developing new technologies for next-generation microprocessors. Sathe led the research and development effort at AMD that resulted in the first-ever resonant clocked commercial microprocessor. In addition, several of his other inventions have been adopted for use in future-generation microprocessors. His doctoral thesis was selected as the best dissertation for 2007 in electrical engineering and computer science at the University of Michigan, Ann Arbor, and was also nominated for the university’s Rackham Graduate School Distinguished Dissertation Award.

Sathe’s group conducts research over a variety of areas covering circuits and architectures for low power computing and biomedical systems. He serves as a member of the Technical Program Committees of the Custom Integrated Circuits Conference and has previously served as a guest editor for the Journal of Solid-State Circuits.

Awards and Honors

NSF CAREER Award 2019

Research Projects

  • Bidirectional Brain Computer Interfaces : Circuits and Architectures (NSF, Medtronic)
  • Runtime computation for advancing integrated circuits and systems (NSF, SRC)
  • Adaptive circuits and architectures for hardware security (NSF, SRC)
  • Power Management : Run-time configurable voltage regulator circuits and architectures (Intel)
  • High-performance, energy-efficient digital circuits and architectures for mm-Wave communication (JCATI, Boeing)

Recent Publications


  • X. Sun, A. Boora, W. Zhang, R. Pamula and V. S. Sathe," A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS", ISSCC 2019
  • F. Rahman, R. Pamula, A. Boora and V. S Sathe, "Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS", ISSCC 2019
  • S. Kim, T. Moreau, P. Howe, A. Alaghi, L. Ceze and V. S. Sathe, "Energy Efficient Neural Network Acceleration under Bit-level Memory Errors", Transactions on Circuits and Systems-1, 2018
  • F. Rahman, S. Kim, N. John, R. Kumar, R. Pamula and V. S. Sathe, "An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor", VLSI Symposium 2018
  • R. Pamula, S. Kim, X. Sun, F. Rahman and V. S. Sathe, "An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS", VLSI Symposium 2018
  • X. Sun, S. Kim, F. Rahman, R. Pamula, X. Li, N. John, and V. S. Sathe, "A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor", ISSCC 2018
  • F. Rahman, G. Taylor, V. S. Sathe, "Computational Locking: Accelerating Lock-times in All-Digital PLLs", VLSI Symposium 2017
  • W. A. Smith, J. P. Uehlin, J. C. Rudell, V. S. Sathe, "A Scalable, Highly-Multiplexed Delta-Encoded Digital Feedback ECoG Recording Amplifier with Common and Differential-Mode Artifact Suppression", VLSI Symposium 2017

Students

Post Doctoral Scholars

  • Rajesh Pamula

Current Students:

  • F. Rahman (PhD)
  • X. Sun PhD)
  • Chi-Hsiang Huang (PhD)
  • Arindam Mandal (PhD)
  • Diego Pena Colaiocco (PhD)
  • Yidong Chen (MS)
  • Tyler Terhune (MS)