A physical implementation of an ASIC design can be produced using one of four general technologies: full custom, standard cell, gate array, or field programmable gate array. The choice of which technology to use depends on design size, desired performance, number of units, and time to market issues. This study presents an analysis of these issues for each technology. To do this, designs were created and implemented in each technology, from which data was gathered and compared. Also, foundries were polled to obtain information on each technology. This study describes the technologies, the circuit designs used to compare them, and the results from the analysis of these issues.
Chapter 3. Circuits
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3.1. Combinational 13
3.2. Sequential 14
3.3. Additional Circuits 17
Chapter 4. Methodology
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Chapter 5. Results
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5.1. Area Results 25
5.2. Performance 27
5.3. Other Issues 29
Chapter 6. Conclusions
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References
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Appendix A. DNA Design Details
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Appendix B. Verilog Code
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Appendix C. Full Custom Implementations
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