The Large Hadron Collider (LHC) is the world's largest particle physics experiment, and it is located at CERN in Geneva, Switzerland. It is a 27km long particle accelerator which takes two protons, brings them to nearly the speed of light and then collides them together inside the detectors of the different experiments stationed around its ring. In total the LHC is comprised of seven separate experiments: ALICE, LHCb, CMS, TOTEM, LHCf, MoEDAL, and ATLAS. Over the past few years the LHC has undergone upgrades it order to increase the energy of the collisons up from 7 TeV to 13 Tev.
The ATLAS experiment (A Toroidal LHC Apparatus) is a massive 7 ton general purpose particle detector investigating the largest range of physics possible. ATLAS is a 4-pi detector which means that the interaction (collision) point is fully surrounded by detector material; this is so to ensure that all possible particle flight paths are detected. Four componenets of ATLAS make this possible: the Inner Detector which is composed of several tracking detectors to track particle movement, the Calorimeters which measure the energy of the particles, the Muon Detectors that detect the Muons and neutrinos which are still able to have energy at such great distances from the interaction point, and the ATLAS trigger system which coordinates the actions and data collection of all sub-detectors.
The Inner Detector of ATLAS consists of three sub-detectors: the Pixel Detector, Semiconductor Tracker (SCT), and Transition Radiation Tracker (TRT). We work on Pixel Detector, the innermost tracking detector, is essential for detecting and tracking particles emerging from collisions. It is made up of four barrel layers (Layer-0 or B-Layer, Layer-1, Layer-2, and the Insertable B-Layer, added in 2014) and six end-cap disks (Disk-1, Disk-2, and Disk-3 on both sides). The Pixel Detector contains over 90 million silicon-based particle detectors (silicon Pixel sensors) distributed across its layers. These sensors function similarly to a high-resolution camera, where a charged particle hitting a pixel deposits an electrical charge that is amplified by the analog circuitry and then processed by the digital electronics. The sensors are connected to specialized Front-End electronics (FE chips), which read out and calibrate the pixel arrays. Once processed, the data is transmitted through the Data Acquisition (DAQ) chain, which includes the Back-of-Crate Card (BOC) for communication with the Front-End electronics and offline storage, and the Readout Driver (ROD), which processes the data, integrates additional ATLAS information, and assembles the data into physics events. Both the BOC and ROD rely on Field-Programmable Gate Arrays (FPGAs) for high-speed data handling. The precision of the Pixel Detector, through its sensors, electronics, and data acquisition systems, plays a critical role in tracking particles and enabling the study of fundamental physics processes.
Our work focuses on FPGA development in the ROD and BOC systems, particularly enhancing the ROD datapath, which handles tasks such as front-end data formatting, event building with front-end data, error checking, and routing to the ReadOut System (ROS) via the BOC for further processing and storage. The Read Out Driver (ROD) and Back of Crate (BOC) are critical components of the readout system, located in a shielded counting room away from the collision site to avoid radiation. Both systems rely heavily on FPGAs for their functionality. The BOC, equipped with three Xilinx Spartan-6 FPGAs, serves as the interface between the detector modules and the ROD, performing opto-electrical conversion, transmitting commands, and forwarding hit data to the ROD. The ROD, composed of four Xilinx FPGAs (including a Virtex-5 and Spartan-6 models), processes data received from the BOC, performing error detection, event building, and histogramming during calibration. The IBL and Pixel layers share the same FPGA-based hardware for their readout systems, though the firmware differs due to variations in front-end chips.
The Yet Another Rapid Readout (YARR) system is a data acquisition (DAQ) framework developed for the ATLAS experiment at CERN. YARR is designed to handle pixel detectors' readout, which is optimized for current and next-generation pixel readout chips (FE chips), including the ATLAS FE-I4 and those developed by the RD53 collaboration.
Currently, we are working with Dr. Timon and the LBNL ATLAS on YARR (Yet Another Rapid Readout) and its firmware. The firmware was developed for the YARR software package and commercial PCIe FPGA cards. The main focus of our work is FPGA development for the YARR-FW maintenance and upgrade. The YARR-FW is responsible for several tasks, including chip configuration, handling trigger signals sent to the readout chips, synchronizing data acquisition, collecting raw data from the pixel readout chips, FE data formatting, and communication with the host. We commonly use Series 7 FPGAs for the YARR readout - specifically the TEF1001(Kintex-7 160T).
This work is done in collaboration with Prof. Hsu and the UW physics department. It is also done in collaboration with several other universities and institutions most notably INFN Bologna who are in charge of ROD development. This work is supported by US ATLAS and well as CERN.